1. Field of the Invention
The present invention relates to a manufacturing method for a semiconductor device, and relates more particularly to a manufacturing method for a semiconductor device having a multilayer interconnect.
2. Description of the Related Art
With the progress in miniaturization and integration of semiconductor devices, the number of interconnect layers has steadily increased. This has resulted in the number of processes required to form the wiring layers and the contact layers for electrically interconnecting the wiring layers accounting for a larger percentage of the total number of processes in the manufacture of a semiconductor device. The method of forming the wiring layers and contact layers thus occupies an extremely important position in the overall semiconductor device manufacturing process.
One technique for easily and simultaneously forming wiring and contact layers is the dual damascene method. The technique that is taught in Japanese Unexamined Patent Application (kokai) 8-17918 is described below as an example of this dual damascene method.
Typical steps in the production of a wiring layer and contact layer using this dual damascene method are shown in FIG. 14 to FIG. 16.
Referring first to FIG. 14, a first insulation layer 120 is formed on a silicon substrate 110 in which a diffusion layer 112 is formed. A silicon nitride layer 130 is then formed over the first insulation layer 120, and a resist layer R3 is formed over the silicon nitride layer 130. There is an opening 170 in the resist layer R3 above a spot where a contact hole 150, further described below, is to be formed. The silicon nitride layer 130 is then etched.
Referring next to FIG. 15, after the resist layer R3 is removed, a second insulation layer 140 is formed over the silicon nitride layer 130 and first insulation layer 120. Another resist layer R4 is then formed on this second insulation layer 140. There is an opening 180 in this resist layer R4 positioned at the area where a trench 152, further described below, is to be formed. The second insulation layer 140 is then etched using the resist layer R4 as a mask to form a trench 152, and the first insulation layer 120 is etched using the silicon nitride layer 130 as a mask to form a contact hole 150.
After first removing the resist layer R4, the contact hole 150 and trench 152 are then filled with a conductive material so as to cover all surfaces thereof. See FIG. 16. The surface is then polished using a chemical-mechanical polishing (CMP) technique to form an embedded wiring layer 160.
It will be appreciated from the above description that a silicon nitride layer 130, which functions as a mask for etching the first insulation layer 120, must be disposed between the first insulation layer 120 and second insulation layer 140 in order to form contact hole 150 and trench 152 with the above method. When a silicon nitride layer 130 is disposed between the first insulation layer 120 and second insulation layer 140, a resistance-capacitance (RC) wiring delay occurs as a result of the high dielectric constant of the silicon nitride layer 130. That is, a delay in signal transmission occurs because of an increase in line resistance and an increase in line capacitance. The presence of an RC wiring delay leads to various problems, including a drop in the processing capacity (e.g., speed) of the semiconductor device, operational errors resulting from cross-talk, and an increase in temperature (heat output) in conjunction with an increase in power consumption.
Therefore, it is an object of the present invention to overcome the aforementioned problems.
A more particular object of the present invention is to resolve the above noted problems by providing a semiconductor device having good electrical characteristics, and by providing a manufacturing method for such semiconductor device.
To achieve these objects, the present invention provides a method for manufacturing a semiconductor device having a plurality of wiring layers, and an insulation layer intervening between wiring layers, and comprises the following steps:
(A) forming an insulation layer on a first wiring layer;
(B) forming in a top part of the insulation layer a wiring trench in an area where a second wiring layer will be formed, and forming in a bottom part of the insulation layer a through-hole in an area where a contact layer for electrically connecting the second wiring layer and first wiring layer will be formed; and
(C) filling a conductive material into the wiring trench and through-hole to integrally form the second wiring layer in the wiring trench with the contact layer in the through-hole.
Step (B) in this method includes the following steps:
(a1) forming a first resist layer with a first photosensitivity characteristic on the insulation layer, the first resist layer having a first opening above an area where the through-hole is to be formed, and
(a2) forming a second resist layer on the first resist layer, the second resist layer having a second photosensitivity characteristic that is different from the first photosensitivity characteristic of the first resist layer, and the second resist layer having a second opening above an area where the wiring trench is to be formed; and
(b) etching the insulation layer and removing the first and second resist layers during the etching of the insulation layer.
The above noted difference in photosensitivity characteristics refers to the difference between a positive resist and negative resist. More specifically, when the first resist layer is a positive resist, the second resist layer is a negative resist; when the first resist layer is a negative resist, the second resist layer is a positive resist.
A wiring trench and through-hole can thus be formed in automatic alignment as a result of the process described below according to the present invention without disposing a silicon nitride layer between insulation layers. More specifically, by etching the insulation layer through the opening in the first resist layer, a trench is formed in the top of the insulation layer and the resist layer is simultaneously removed. When the first resist layer not covered by the second resist layer is removed, the shape of the trench is the shape of the through-hole to be formed. As etching of the insulation layer continues, the insulation layer (where the wiring trench is formed) is etched through the opening in the second resist layer while maintaining the shape of the trench. When the bottom of the trench is etched to the first wiring layer, a wiring trench is formed in the top part of the insulation layer and a through-hole is formed in the bottom of the insulation layer. It is thus possible to form a wiring trench and through-hole without a silicon nitride layer intervening in the insulation layer, and steps for forming a silicon nitride layer and then forming an opening in the silicon nitride layer can be omitted.
It should be noted that with the manufacturing method of the invention the angle formed by the bottom of the wiring trench and the side wall of the through-hole is substantially a right angle.
It should be further noted that the depth ratio between the through-hole and wiring trench can be controlled by appropriately controlling the resist layer configuration (particular the layer thickness of the first resist layer and second resist layer), and etching conditions (such as the relative selectivity of the resist layers and insulation layer).
A semiconductor device resulting from this manufacturing method does not have a silicon nitride layer intervening between insulation layers. As a result, the dielectric constant between a first wiring layer and second wiring layer can be held to that resulting only from the insulation layer between wiring layers. The RC wiring delay can therefore be kept to the absolute minimum.
In the manufacturing method of the invention, steps (a1) and (a2) for forming the first and second resist layers comprise:
(c) forming the first resist layer on the insulation layer;
(d) exposing a part of the first resist layer;
(e) forming the second resist layer on the first resist layer;
(f) exposing a part of the second resist layer;
(g) developing the second resist layer and forming the second opening; and
(h) developing the first resist layer and forming the first opening.
It should be noted that step (h) can be performed either before step (e) or after step (g).
The developer used in resist layer development step (g) is preferably a developer that will not remove the first resist layer. Further preferably, the developer used in resist layer development step (h) is a developer that will not remove the second resist layer.
Yet further preferably, the etchant used for etching in step (b) is a mixed gas containing a CF gas. This CF gas is yet further preferably one or more of the following: CF4, CHF3, C2F6, C4F8, and C5F8. Yet further preferably, the mixed gas containing a CF gas contains at least one of the following: CO, Ar, O2, and N2.
The conductive material used to fill the wiring trench and through-hole preferably contains aluminum or copper.
It should be noted that the first wiring layer in a semiconductor device according to this invention includes a first, second, or subsequent wiring layer, or a conductive part of a semiconductor element such as a gate electrode or diffusion layer formed on a substrate surface.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.